1. Field of the Invention
The present invention is generally related to a semiconductor device fabrication technique, and more particularly, to a method for reducing the difference in level between an STI isolation (which may be simply referred to as an “STI” region) and an active device region (which may be simply referred to as an ‘ACTIVE’ region) in a wafer and a system for implementing the method in an efficient manner.
2. Description of the Related Art
Various techniques for achieving flat and even surfaces of STI regions in a semiconductor wafer have been proposed and employed in semiconductor device fabrication technologies because uneven surfaces of STI regions make gate electrode (and/or gate line) patterning difficult. For example, JP 11-340315A discloses a technique for forming a shallow trench isolation (STI) region having a flat surface by preventing undesirable depressions from being produced along the edges of the STI region. According to this method, an oxide film is formed on a silicon (Si) substrate by thermal oxidation, and a silicon nitride stopper film is formed over the oxide film. Then, specific areas of the stopper film, the oxide film, and the Si substrate are successively removed by selective etching using a photolithography technique, thereby forming an STI trench. A thermally oxidized film is formed on the inner surface of the STI trench, and then oxide is deposited on the entire surface, thereby forming a buried oxide film filling the STI trench. The buried oxide film is polished by chemical mechanical polishing (CMP) until the SiN stopper film is exposed, and then the SiN stopper film is removed by a phosphoric acid etchant. A portion of the buried oxide film remains projecting from the STI trench. The side walls of the projecting portion of the buried oxide film are then covered with a side-wall oxide film, and the projecting portion of the buried oxide film is removed together with the side-wall oxide film by isotropic etching so as to flatten the STI region. Thus, it is possible to prevent depressions from being produced along the edges of the STI region in the flattening process.
Meanwhile, JP 2002-151465A discloses a technique for reflecting the wafer conditions in the wafer processing parameters by a feed-forward system to guarantee stable qualities of semiconductor devices. With this technique, the thickness of the buried oxide film is measured and fed forward to the subsequent process to determine the etching condition or other processing conditions.
The STI region forming method of the former publication (JP 11-340315A) can prevent local depressions at the edges of the STI region from being produced, but cannot prevent an indentation across the entire surface of the STI region from being formed unless such wafer conditions are fed forward to reflect the presence of the indentation in determining the etching amount of the buried oxide film.
Although the feed-forward technique of the latter publication (JP 2002-151465A) measures the thickness of the buried oxide film and feeds the measurement result forward to the subsequent process, this technique does not take into account the fact that the degree of the surface indentation varies depending on the area of the STI region, as illustrated in FIG. 1A and FIG. 1B. In these figures, an oxide film 12 and a SiN stopper film 13 are formed in this order over a silicon (Si) substrate 11. A buried oxide film 15 is formed in an STI trench 16 which is formed by partially removing the SiN stopper film 13, the oxide film 12 and the silicon substrate 11.
When CMP is performed to flatten the buried oxide film 15 in the STI trench 16, the STI region is polished more deeply at the center than the edges due to the polishing-rate difference between the buried oxide film 15 and the SiN stopper film 13. The wider the area of the STI region, the deeper the surface indentation at the center of the STI region is, as illustrated in FIG. 1A. That is, a depth d1 of the indentation of the wide STI region (FIG. 1A) is greater than a depth d2 of the indentation of the narrow STI region (FIG. 1B) (d1>d2). In the illustrated examples, the difference between d1 and d2 is 5 nm or greater.
If a wafer has a surface level difference of 5 nm or greater due to the difference of the area between STI regions, the focal position varies during the exposure process, and the resultant gate width (i.e., the longitudinal size of the gate electrode patterned on the wafer) varies about 6 nm. In general, measurement of the thickness of a buried oxide film is carried out using a wide STI region prepared especially for the measurement purpose taking into account the diameter of the irradiation beam spot. However, the area of an STT region of a part where a transistor is actually formed is very small. If the surface level of the STI region of the actual transistor region is controlled based on the thickness of the buried oxide film measured using the wide STI region area, because the referenced measured value is smaller than the thickness of the actual buried oxide film, the resulting surface level difference between the STI region and the ACTIVE region in the transistor region is large. This results in making gate electrode patterning difficult and reducing production yield of semiconductor devices.
In the future, if the gate electrode width is reduced, reduction of production yield may be inevitable. Moreover, the depths of trenches in a STI region of a wafer largely vary, so that a level difference is produced between the STI region and the ACTIVE region even if the thickness of the buried oxide film is referred to.
The above described semiconductor device fabrication methods do not take into account variations between fabrication lots in the processes preceding CMP. Variations include (1) a variation of the thickness of the SiN stopper film 13 (FIGS. 1A and 1B) due to variations in the condition of a furnace or due to a variation between batches in the process of depositing the SiN stopper film 13 (e.g. 25 pieces×6 lots=150 pieces processed per batch), (2) a variation of the thickness of the SiN stopper film 13, which is dependent on the lifetime of SPM solution used for etching of the SiN stopper film 13 during SPM cleaning after dry etching (the longer the lifetime, the greater the etching amount of the SiN stopper film 13), and (3) a variation of the thickness of the SiN stopper film 13 after CMP.